1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which static memory (SRAM) circuits are integrated on a semiconductor chip. More particularly, the present invention relates to a configuration for reducing a standby current in an SRAM integrated circuit device and a configuration for operating the SRAM integrated circuit device at a low supply voltage.
2. Description of the Related Art
Japanese Patent Laid-Open No. 7-296587 discloses a circuit for reducing a standby current by using a resistance to make a source line potential of a driver transistor in an SRAM memory cell higher than a ground potential. Japanese Patent Laid-Open No. 2002-197867 discloses a circuit for reducing the standby current by using a diode to make the source line potential of the driver transistor in the SRAM memory cell higher than the ground potential. Japanese Patent Laid-Open No. 5-120882 discloses a circuit for reducing a leakage current flowing through transfer MOS by applying a voltage lower than the ground potential to a word line of the memory cell that is not accessed in the SRAM circuit.
As an electric power consumption of an LSI (Large Scale Integrated Circuit) is reduced and transistors in the LSI become smaller more and more, a supply voltage of the LSI is also reduced. For example, in the case of 0.13 ìm process, the LSI operating with supply voltage of 1.2 V is manufactured. If the supply voltage of the LSI is reduced, in order to prevent circuit performance (an operational speed of the circuit) from deteriorating, a threshold voltage (Vth) for the transistors is reduced so as to increase a current for the transistors and, for example, in the 0.13 ìm process, MOS transistors with Vth of about 0.4 V are used. In transistors with low Vth, a current that flows between source and drain when the transistors are OFF and that is referred to as a subthreshold current is increased. This current flows continuously even when the circuit comprised of the related transistors is not operating and, therefore, it is consumed continuously even in the state in which the LSI is energized but not operating (hereinafter referred to as “the standby state”). In a logic circuit in which data is not saved, the leakage current can be inhibited by shutting off the power supply in the standby state but, in a memory circuit in which data must be saved even in the standby state, the power supply cannot be shut off even in the standby state. Thus, there is a problem in that the subthreshold current is increased and, therefore, the electric power consumption in the standby state is also increased as Vth of the transistors constituting the circuit is reduced.
It has conventionally been considered effective to reduce the leakage current by applying a back-gate bias to increase Vth of the MOS transistors but, when the back-gate bias is applied to the MOS transistors manufactured in a microfabrication process, a potential between drain and back-gate may be increased and, as a result, a leakage current called a junction leakage may be increased. When the junction leakage is increased, the leakage current may not be reduced even though the subthreshold leakage is reduced by increasing the Vth with the aid of the back-gate bias. In the SRAM circuit, by making the source line potential of the driver MOS in the memory cell higher than the ground potential, a substrate bias effect can be applied to the transfer MOS and the driver MOS so as to reduce the leakage current significantly. In this case, though the substrate bias is applied, the potential between drain and back-gate does not differ from the one when the substrate bias is not applied and, therefore, the junction leakage current is not increased.
However, considering the fact that a circuit for controlling the potential itself consumes an amount of current and, if the circuit for controlling the potential is designed so that it consumes less current, it may be very susceptible to manufacturing variations in transistors and so on, there is a problem in that the reduction of the leakage current may become less effective.
As the manufacturing process of the MOS transistors becomes finer, the variation of Vth in the transistors tends to be increased. In the SRAM circuit having a large variation of Vth, there is also a problem in that it is impossible to write to the memory cell if Vth of the transfer MOS is increased and Vth of the load MOS is reduced.